Large scale integrated semiconductor devices include semiconductor memory devices and semiconductor logic devices. Many of these semiconductor devices employ MOSFETs (metal oxide semiconductor field effect transistors) due to their manufacturability and performance to provide highly integrated circuits. Semiconductor memories include DRAMs (dynamic random access memories) and SRAMs (static random access memories). DRAMs provide a smaller bit/area and thus have reduced costs and are employed in a variety of data storage applications.
A DRAM includes a plurality of memory cells arranged in an array configuration. Each memory cell includes a memory cell transistor and a memory cell capacitor (capacitor element). Information is stored in a memory cell by storing electric charges on a memory cell capacitor. A memory cell transistor is turned on to select a memory cell to provide access to the memory cell capacitor to read data from or write data to the memory cell capacitor. A memory cell transistor in a DRAM is typically a MOSFET.
As is well known, a MOSFET includes a source area and a drain area, both being formed with a predetermined conductivity type on a semiconductor substrate. A MOSFET also includes a gate electrode formed on a gate insulating film over a channel area between the source area and drain area. An impedance path between the source area and drain area is controlled by applying a control voltage to the gate electrode. In this way, the conductivity of the channel area is controlled.
Japanese Patent Laid-Open No. 66861/1985 discloses a manufacturing method for a conventional MOSFET. FIGS. 1A-1C are cross-sectional views illustrating various processing steps for a conventional MOSFET as disclosed in Japanese Patent Laid-Open No. 66861/1985.
Referring now to FIG. 1A, a selective oxidation method is used to form a field oxide film 102 on the surface of a P-type silicon substrate 101. A CVD oxide film 103 and gate oxide film 104 are then formed on a device formation area. A gate electrode 105 is then formed on a side wall of CVD oxide film 103 to cover a part of gate oxide film 104.
Referring now to FIG. 1B, CVD oxide film 103 and gate oxide film 104 are etched and removed to leave behind only gate electrode 105 and gate oxide film 104 located just under gate electrode 105. An N-type impurity, such as arsenic (As), for example, is then implanted with a low dose through ion implantation using gate electrode 105 as a mask.
Referring now to FIG. 1C, a CVD oxide film 106 is then formed on a side wall of gate electrode 105. Then an N-type impurity, such as arsenic (As), for example, is implanted with a high dose through ion implantation using gate electrode 105 and CVD oxide film 106 as a mask. The ion doped arsenic is then diffused by being subjected to a heat treatment to form a LDD (lightly doped drain) structure MOSFET including an N+ type (high concentration N-type conductivity) area and an N− type (low concentration N-type conductivity) area.
The conventional manufacturing method for a semiconductor device as described above has a drawback in that the source area and the drain area are both formed with the same impurity concentration distribution. By doing so, the performance when operating in in some applications may be limited.
In the conventional manufacturing method for a MOSFET disclosed in Japanese Patent Laid-Open No. 66861/1985, the source area and drain area are formed in the same process by implanting an impurity ion in a common process step. By doing so, the impurity concentration distributions in these areas are symmetrical. In this case, the source area and the drain area are compatible with a basic or typical performance of a MOSFET. However, in some applications a MOSFET having impurity concentration distributions that are the same in the source area and drain area may have drawbacks.
In light of the above discussion, it would be desirable to provide a semiconductor device including an insulated gate field effect transistor (IGFET), such as a MOSFET, that includes a source/drain area that has a lower impurity concentration distribution than the other source/drain area. It would also be desirable to provide such an IGFET in a memory cell of a semiconductor memory device, such as a DRAM. It would also be desirable to provide a manufacturing method for the semiconductor device.